Description: 基于IEEE802.11n标准,采用verilog语言设计的(2,1,7)卷积码viterbi译码器,支持1/2,2/3,3/4,5/6四种码率的译码,以测试无误-IEEE802.11n standard Verilog language design (2,1,7) convolutional code viterbi decoder support 1/2, 2/3, 3/4, 5/6 four bit rate decoding to test and correct Platform: |
Size: 18432 |
Author:logic |
Hits:
Description: 卷积码是一种重要的前向纠错信道编码方式，其纠错性能常常优于分组码，且(2,1,7)卷积码已应用于现代卫星通信系统中。Viterbi译码算法能最大限度地发挥卷积码的优异性能。这里采用Verilog HDL语言设计出(2,1,7)卷积码的编码器模块和基于Viterbi算法的译码器模块，译码器采用全并行结构，译码速度快-Convolutional code is an important forward error correction channel coding method, and its error correction performance is often better than the block code, and (2,1,7) convolutional code has been used in modern satellite communication system. Viterbi decoding algorithm can maximize the performance of convolutional codes. Here is the Verilog HDL design (2,1,7) convolutional code encoder module and decoder module based on Viterbi algorithm, the decoder is designed using the parallel structure and the decoding speed is fast. Platform: |
Size: 10240 |
Author:邓博于、 |
Hits:
Search - Viterbi Decoder 2.1.7